Monthly Archives: October 2014

Next revision of SystemVerilog standard will not start until at least March 2015

Standard

Update: The (unapproved) meetings of the March 2015 meeting are here.

Following up to “Is it time for another revision of SystemVerilog”, according to the Oct. 7 minutes the next meeting will “be scheduled in or around DVCon San Jose 2015” in March 2015.

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