Is it time for another revision of SystemVerilog?


The chair of the IEEE P1800 working group for SystemVerilog recently sent an email announcing a meeting on Oct. 7, 2014 with this agenda. Of special interest is item 6, as follows

6) P1800 next steps

  • The IEEE has expanded the number of years between required ratification of a standard to 10, we are currently at 2
  • There are a number of standards efforts enhancing specification that are benefiting from SystemVerilog stability
  • There have not been many bug reports or activity on the current standard
    • There has been a few questions around when work will resume
  • What path should we take with respect to remaining on hold, or considering a new PAR


Finally, here’s my attempt at a joke by taking a comment completely out of context



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